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Microcontroller Kits Simple
Mikrokontroller 89s51 Trainer All Item Include
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5.1. Interrupt
The 80C51 provides 5 interrupt sources. These are shown
in Figure 17. The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits IT0 and IT1
in Register TCON. The flags that actually generate these interrupts are
bits IE0 and IE1 in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when the service routine
is vectored to only if the interrupt was transition-activated. If the
interrupt was level-activated, then the external requesting source is
what controls the request flag, rather than the on-chip hardware. All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be canceled in software. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE (Figure 18). IE also contains a global disable bit, EA, which disables all interrupts at once. Priority Level Structure Register IP (Figure 19). A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two request of different priority levels are received
simultaneously, the request of higher priority level is serviced. If requests
of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus within each priority
level there is a second priority structure determined by the polling sequence
as follows: Note that the “priority within level” structure is only used to resolve simultaneous requests of the same priority level. The IP register contains a number of unimplemented bits. IP.7, IP.6, and IP.5 are reserved in the 80C51. User software should not write 1s to these positions, since they may be used in other 8051 Family products.
Interrupt Priority Register ( IP )
Note:
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